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45 lines
993 B
Makefile
45 lines
993 B
Makefile
################################################################################
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# Automatically-generated file. Do not edit!
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################################################################################
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-include ../makefile.init
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RM := rm -rf
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# All of the sources participating in the build are defined here
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-include sources.mk
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-include src/subdir.mk
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-include subdir.mk
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-include objects.mk
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ifneq ($(MAKECMDGOALS),clean)
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ifneq ($(strip $(C_DEPS)),)
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-include $(C_DEPS)
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endif
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endif
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-include ../makefile.defs
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# Add inputs and outputs from these tool invocations to the build variables
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# All Target
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all: wordsearch
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# Tool invocations
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wordsearch: $(OBJS) $(USER_OBJS)
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@echo 'Building target: $@'
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@echo 'Invoking: GCC C Linker'
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gcc -o "wordsearch" $(OBJS) $(USER_OBJS) $(LIBS)
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@echo 'Finished building target: $@'
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@echo ' '
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# Other Targets
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clean:
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-$(RM) $(EXECUTABLES)$(OBJS)$(C_DEPS) wordsearch
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-@echo ' '
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.PHONY: all clean dependents
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.SECONDARY:
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-include ../makefile.targets
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